Semiconductor packaging typically involves encapsulating or housing a semiconductor component or device, for example a semiconductor chip, within a device carrier or substrate. The device carrier or substrate supports the semiconductor chip and facilitates a convenient handling of the semiconductor chip. In addition, the device carrier comprises external connections or terminals for electrically connecting the semiconductor chip to an external circuit.
A known method of semiconductor packaging, more specifically a method of forming a flip-chip on leadframe (FCOL) semiconductor package, employs a plated leadframe. A leadframe is a patterned sheet of metal. The sheet of metal, which is typically copper, is commonly plated with one of silver, nickel or palladium. Plating is necessary to prevent the sheet of metal from oxidizing, and to provide a surface onto which solder will adhere or, when employing wire bonding, gold or aluminum can be bonded. The pattern of the sheet of metal provides a leadframe for forming the FCOL semiconductor package.
Typically, leadframes for forming FCOL semiconductor packages have leads with inner lead portions and outer lead portions. The inner lead portions are arranged in a pattern with interconnect locations on the inner lead portions matching pattern of pads formed on a surface of the semiconductor chip. Solder bumps or balls are deposited on the pads formed on the surface of the semiconductor chip. Reflow of the solder bumps facilitates bonding of the pads of the semiconductor chip with the leadframe, more specifically with the interconnect locations on the inner lead portions of the leadframe.
The semiconductor chip is then placed on the leadframe with the pads of the semiconductor chip abutting the interconnect locations on the inner lead portions of the leadframe. Assembly of the semiconductor chip and the leadframe is then heated to an elevated temperature to reflow the solder bumps for forming solder interconnects between the semiconductor chip and the leadframe. The heating of the assembly is typically performed in a heating chamber or oven. The resultant semiconductor package formed is known in the art as the FCOL semiconductor package.
Current heating processes for reflowing the solder bumps as described above have been considered to be significantly time consuming, thereby impairing fabrication or manufacturing efficiency and throughput of semiconductor packages.
In addition, coefficient of thermal expansion (CTE) of the semiconductor chips generally differs from CTE of the leadframes or other substrates. Accordingly, differential expansion occurs between the semiconductor chip and the leadframe when the assembly of the semiconductor chip and the leadframe is heated. The differential expansion between the semiconductor chip and the leadframe can cause mis-alignments between the solder bumps on the pads of the semiconductor chips and the solder bumps on the inner lead portions of the leadframe, thereby resulting in impaired or malfunctioning solder interconnects between the semiconductor chip and the leadframe. Such mis-alignments and impaired solder interconnections are especially prevalent with semiconductor chips or packages having a fine pitch.
The increasing functionality, speed and portability of modern electronic devices have resulted in an increasing need for more electronic components or elements to be integrated into the semiconductor chip. Accordingly, reduction of the pitch or distance between adjacent pads or electrical interconnects, and between the solder bumps formed thereon, of the semiconductor chip is increasingly important in the semiconductor industry.
However, the reduced pitch or distance between pads or electrical interconnects of the semiconductor chip increases risk, and occurrences, of bridging between the adjacent pads or electrical interconnects, thereby resulting in electrical shorting.
Correspondingly, the increased risk, and occurrences, of electrical shorting between adjacent pads or electrical interconnects adversely affects the reliability and quality of the fabricated semiconductor packages.
Accordingly, a person skilled in the art will appreciate that an improved method for fabricating flip-chip semiconductor packages capable of addressing at least one of the above-identified issues is needed.